Metastability Analysis of Synchronizer
Keywords:
Data Synchronization, Data Loss, Data Loss Metastability, SynchronizerAbstract
The multiple clock domain systems communicate with each other causes data loss. This data loss is due to mismatch in frequencies. For proper communication the frequencies must be synchronized. Hence synchronizer is used for data synchronization process with non-zero probability of failure. The synchronizer is also having its parameters. It suffers from metastability as data changes in between timing window due to which synchronizer failure occurs. As the metastability occurs we cannot predict the correct level at output. The proposed architecture is modeled with verilog and simulated with Xilinx ISE design suit 13.1and its parameter are verified with Quartus II 10.1. Analog behavior is studied by using Tanner. The probability of occurrence of metastability reduces with timing window width.
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