Realization of FIR Filter using Distributed Arithmetic Architecture

Abstract

This work represents an efficient implementation of Finite Impulse response (FIR) filter using Distributed Arithmetic (DA) architecture. Distributed Arithmetic (DA) architecture is an efficient technique for calculation of inner product or multiply and accumulate (MAC) using Look-up tables. In absence of DA, the direct method of implementing MAC uses dedicated multipliers which are fast but consume considerable hardware. MAC operation is common in digital signal processing algorithms. Here DA replaces the explicit multiplications by ROM look-up tables which is an efficient technique to implement on FPGA. To save the memory units, we have divided the look-up tables. Area saving from using DA can be up to 80% in DSP hardware design. This work shows the implementation of an eight order FIR filter using DA architecture through VHDL coding and the code is finally simulated using Modelsim and then compared with MATLAB output.